1. Field of the Invention
The present invention relates to the fabrication of a wafer-level flip chip package by use of a pre-coated anisotropic conductive adhesive.
2. Description of the Prior Art
Involved in all procedures of the production of final products from semiconductor devices, an electronic packaging technology is a system fabrication methodology covering a wide range of versatile techniques. With great advances in technology in recent years, semiconductor fabrication techniques have enabled the integration of million or more cells, the multiplication of I/O pins, the enlargement of die sizes, the rapid radiation of large amounts of heat, the high electrical performance of semiconductor devices, etc. The electronic packaging technology, which is to encapsulate these semiconductor devices in some form of hermetically sealed package so as to protect them from external or internal damages, however, cannot keep up with the semiconductor fabrication techniques, which make daily progress.
In determining the performance, dimension, price and reliability of a final semiconductor device product, the electronic package technology is one of the most important factors. Extremely small package parts find numerous applications in the computer, information and communication, mobile communication, and high-end household electrical appliance industries for seeking high electrical and electronic performance, slimness/high integration, low power consumption, multi-functionality, high speed signal processing, and permanent reliability. A flip-chip technique, which is generally used to mount a semiconductor chip onto a circuit board, is extending its applications to the fields of smart cards, displays such as LCD and PDP, computers, mobile phones, communication systems, etc. The flip-chip technique, however, has a drawback in that the production efficiency is poor in terms of process complexity and product cost because it requires conventional solder-using complex connection processes, that is, solder flux coating, chip/board arranging, solder bump reflowing, flux removing, underfiller-filling and curing processes.
In order to reduce these complex processes, particular attention has recently been paid to wafer-level packaging techniques in which wafers are coated with polymeric materials having flux and underfiller functions and processed. More recently, in developing new, improved flip-chip connection techniques, advantage has been taken of conductive adhesives, which are of lower price than solders and enable the formation of ultra fine electrode pitches with the potential to realize environmentally-friendly, fluxless processes and low temperature processes.
Consisting fundamentally of conductive particles such as nickel, gold/polymer, silver, etc. and binders such as thermosetting or thermoplastic insulating resins, conductive adhesives are largely divided into anisotropic conductive adhesive/films and isotropic conductive adhesives. There has been a strong demand for the development of a process of producing a low-priced adhesive and a flip-chip bonding process capable of such a low-priced adhesive. In this connection, based on highly curable, thermosetting epoxy resins, anisotropic conductive adhesive (ACA) is developed. ACA can be divided into anisotropic conductive adhesive films (ACAF) and anisotropic conductive adhesive paste (ACAP) in a view of morphology with preference to ACAP owing to its simpler preparation and more convenient use in the connection processes.
In spite of extensive active research, developed flip-chip techniques using these environmentally-friendly anisotropic conductive films or paste as connecting materials suffer from the disadvantage of being inefficient in production costs because of requiring many processes, including chip designing and bump forming processes for package of ACA flip chips, mass production of connecting materials, and automation of connecting processes.
Many prior arts refer to the flip chip techniques relevant to the present invention.
For example, U.S. Pat. No. 5,323,051, titled xe2x80x9cSemiconductor Wafer Level Packagexe2x80x9d, issued on Jun. 21, 1994, discloses that a cap wafer is bonded to a semiconductor substrate wafer using a glass adhesive, followed by dicing of the wafer into individual chips. This reference patent is quite different from the present invention in which ACA is applied on a wafer and used for package connection.
U.S. Pat. No. 5,918,113, titled xe2x80x9cProcess for Producing a Semiconductor Device Using Anisotropic Conductive Adhesive, issued on Jun. 29, 1999, describes the production of a semiconductor device by forming ACA on a circuit board and heat-pressing a semiconductor chip against the circuit board to achieve an electrical connection therebetween. An obvious difference exists between the reference patent and the present invention in which ACA is coated on semiconductor chips with non-solder bumps formed on their I/O pads.
Another technique can be found in S. H. Shi, T. Yamashita and C. P. Wong, xe2x80x9cDevelopment of the Wafer Level Compressive-Flow Underfill Process and Its Required Materialsxe2x80x9d, 1999 ECTC, pp. 961-966. In the report, an underfiller having a solder flux function is applied onto a solder bump-formed wafer, which is then diced into individual chips, followed by arranging the chips on a substrate with the help of SMT assembly equipment. Certainly, this process is far simpler than a conventional process of filling an underfiller between the chips and the substrate after the solder reflow connection. On the other hand, the present invention can apply the simplification to wafers on which not only solder bumps, but also non-solder bumps, such as electrolyzed or stud gold bumps and electroless nickel or copper bumps, are formed, by use of ACA. An ACA film or adhesive solution is coated onto a non-solder bump formed semiconductor substrate wafer which is then diced into individual chips, immediately followed by the heat-pressing of the individual chips against the circuit board so that an electrical connection is obtained between the chips and the circuit board via the conductive adhesive.
As mentioned above, electronic packaging technology has the task of developing new electrical connections substituting for conventional solder connections in pursuit of environmentally friendly processes as well as lowered production costs.
Therefore, it is an object of the present invention to overcome the problems encountered in prior arts and to provide a method for fabricating a wafer-level flip-chip package, which is advantageous in terms of production cost by simplifying the processes subsequent to the fabrication of conventional solder bump flip-chip packages, including solder flux coating, flip chip/substrate arranging, solder reflowing, flux removing, underfiller filling, and curing processes.
Based on the present invention, the above object could be accomplished by a provision of a method for fabricating a wafer-level flip chip package using anisotropic conductive adhesive, comprising the steps of: forming a low-priced non-solder bump on an I/O pad of each chip of a wafer; coating the anisotropic conductive adhesive over the wafer; dicing the anisotropic conductive adhesive-coated wafer into individual chips by use of a wafer dicing machine; and subjecting the individual chips to flip-chip bonding.